Re: adenine is up (fwd)

From: Adams Kevin J (kevin.adams@PHS.COM)
Date: Tue May 27 2003 - 14:12:40 EDT


Sorry for the confusion.

Yes, it's part of IBM's perfpmr data collection tool. Should have said that.

/usr/bin/lsc is a soft link to ./perf433/lsc.

It can be found at:

ftp://ftp.software.ibm.com/aix/tools/perftools/perfpmr

Kevin Adams

-----Original Message-----
From: Chris Leven [mailto:Chris.Leven@GARLOCK.COM]
Sent: Tuesday, May 27, 2003 10:49 AM
To: aix-l@Princeton.EDU
Subject: Re: [aix-l] adenine is up (fwd)

lsc is not a valid command is it part of some performance monitoring package
or is it an alias?

Christopher Leven
Senior Programmer/Analyst
IBM Certified Specialist AIX Administration
IBM Certified Specialist AIX Support
IBM Certified Specialist RS6000/SP - PSSP 3.1

Garlock Sealing Technologies
An EnPro Industries Company
1666 Division Street
Palmyra, New York 14522
*Voice: 315.597.3034
*Fax: 315.597.7250
*Email: Chris.Leven@Garlock.com

-----Original Message-----
From: Adams Kevin J [mailto:kevin.adams@PHS.COM]
Sent: Tuesday, May 27, 2003 1:34 PM
To: aix-l@Princeton.EDU
Subject: Re: adenine is up (fwd)

You can get similiar output via lsc command.

# lsc
Please wait while we determine the processor megahertz rate ...
attribute value description

architecture PowerPC Processor architecture
implementation Pulsar Processor Implementation
version PowerPC_RS64III Processor version
clock_speed 750.8 CPU clock speed in MHz (approximation)
width 64 Processor width (bits)
ncpus 8 Number of CPUs
realmem 8388608 Amount of usable real memory (Kilobytes)
cache_attrib 1 Split instruction and data cache
icache_size 128 L1 instruction cache size (Kilobytes)
icache_asc 2 L1 instruction cache Associativity
icache_block 128 L1 instruction cache block size (bytes)
icache_line 128 L1 instruction cache line size (bytes)
dcache_size 128 L1 data cache size (Kilobytes)
dcache_asc 2 L1 data cache Associativity
dcache_block 128 L1 data cache block size (bytes)
dcache_line 128 L1 data cache line size (bytes)
L2_cache_size 8192 L2 cache size (Kilobytes)
L2_cache_asc 1 L2 cache associativity
tlb_attrib 3 Combined instruction and data TLB
tlb_size 512 TLB size (entries)
tlb_asc 4 TLB associativity
resv_size 128 Size of reservation (bytes)
priv_lck_cnt 0 Spin lock count in supervisor mode
prob_lck_cnt 0 Spin lock count in problem state
rtc_type RTC_POWER_PC RTC type
virt_alias 0 Hardware aliasing not supported
cach_cong 0 Number of page bits for cache synonym
Xint 78125 Used in time base conversion
Xfrac 58749 Used in time base conversion

Kevin Adams
PacifiCare Behavioral Health
Principal Systems Analyst
AIX Certified Advanced Technical Expert

-----Original Message-----
From: N. Leenders [mailto:nadine@UALBERTA.CA]
Sent: Tuesday, May 27, 2003 9:33 AM
To: aix-l@Princeton.EDU
Subject: Re: [aix-l] adenine is up (fwd)

Hi,
I'm wondering how to get information similar to the following from my
machine:

POWER 3 Processor
    Clock speed
                                    375MHz
    FP Results/Clock
                                    4
    Peak Performance
                                    1.5 Gflops
    L1 Instruction Cache
                                    32 KB
    L1 Data Cache Line Size
                                    128 bytes
    L1 Data Cache
                                    64 KB
    L2 Cache
                                    8192 KB

Thanks, Nadine

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